1. Field of the Invention
This invention relates to the transmission of data and, more particularly, to receivers capable of receiving differential input signals and generating low duty cycle distortion, single-ended output signals regardless of variations in PVT (process, voltage and temperature) and input common mode voltage.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
The transmission of data involves sending and receiving data over a transmission path, which is connected between a pair of transceivers. Each transceiver can have a receiver and a transmitter (or driver). In this manner, the receiver functions to receive data from the transmission path, whereas the transmitter functions to drive data onto the transmission path. The transfer of data between receiver and transmitter circuits fabricated on separate chips is sometimes referred to as “off-chip” signaling or “chip-to-chip” communication.
Single-ended signals are typically used for on-chip communication because of the reduced area consumption and design complexity generally involved in routing these signals. However, more and more off-chip signals, or signals used for chip-to-chip communication, are routed as differential signals because of their decreased sensitivity to environmental noise. For this reason, numerous transmission protocols such as Low Voltage Differential Signals (LVDS), Stub Series Terminated Logic (SSTL), differential High-Speed Transceiver Logic (HSTL) and Low Voltage Positive Referenced Emitter Coupled Logic (LVPECL) have been established for sending and receiving differential signals across a transmission path. These differential signals often have smaller amplitudes (i.e., reduced swings) to facilitate easier routing in high speed chip-to-chip communications. In addition, the common mode voltage (i.e., the average voltage value) of the differential signals often varies significantly from case to case depending on the actual application environment.
A differential to single-end receiver essentially operates as a differential sense amplifier that can ideally accept a relatively wide input common mode voltage range with a high common mode rejection ratio. However, as with most circuits, a practical sense amplifier has a limit as to the common mode voltage that it can accept. Most conventional sense amplifiers are rated based on the common-mode voltage range they can accept and still remain operational. Thus, many sense amplifiers are rated as either accepting of a relatively high common-mode voltage range or a relatively low common-mode voltage range.
For example, IEEE Std. 1596 is a transmission protocol that utilizes low voltage differential signals (LVDS) which, in some cases, may be as low as 200 mV swing compatible with low voltage MOS, BiCMOS, Bipolar, and GaAs receiver circuitry. The interface standard also specifies a maximum voltage (e.g., approximately 2.4 volts) and a minimum voltage (e.g., approximately 0 volts) of differential signal inputs that are acceptable to LVDS receivers. At relatively low differential swings (e.g., about 200 mV to about 300 mV swing), an LVDS receiver may be rated as one that receives both a high and a low common mode voltage. At somewhat higher differential swings (e.g., greater than about 400 mV), however, the input common mode voltage of the differential signals may extend beyond the optimum operating range of the LVDS receiver. Such large variations in input common mode voltage tend to produce severe duty cycle distortion in the single-ended signal output from the LVDS receiver. In some cases, variations in process, temperature and voltage (PVT) may also adversely affect the output duty cycle.
In general, the “duty cycle” of a signal may be described as the ratio of high time (i.e., the time over which the signal is high) to the overall period of the signal. Though duty cycle specifications are often application-specific, desirable duty cycle values may range between about ±2-5% of 50%. In some cases, “duty cycle distortion” may occur when there are time delay differences between: (i) the rising edges of the input and output signals, (ii) the falling edges of the input and output signals, (iii) the rising edge of the input signal and the falling edge of the output signal, or (iv) the falling edge of the input signal and the rising edge of the output signal. In particular, duty cycle distortion may occur between (i) and (ii) if the output signal is not inverted, and between (iii) and (iv) if the output is inverted. In some cases, duty cycle distortion (“DCD”) may be further described as the difference between the output duty cycle (e.g., Y %) and the input duty cycle (e.g., X %), or (Y-X) %. Acceptable levels of duty cycle distortion may range between about 0% DCD and about 10% DCD, depending on the application.
Consequently, a need exists for an improved differential-to-single-ended receiver capable of receiving differential signals over a full range of input common mode voltages and generating low duty cycle distortion, single-ended signals that are insensitive to variations in PVT and input common mode voltage.